package diffast-langs-verilog
sectionYPositions = computeSectionYPositions($el), 10)"
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Verilog parser plugin for Diff/AST
Install
dune-project
Dependency
Authors
Maintainers
Sources
v0.3.5.1.tar.gz
sha256=6971a07313d308bdfcfe165fd76c218454826fe594acfa6ab25b0e7a1c739cb5
md5=be0348ed663151930bc8ced0ca678b60
doc/diffast-langs-verilog.base/Verilog_base/V_label/Statement/index.html
Module V_label.StatementSource
include module type of struct include Ls.Statement end
Source
type t = Verilog_parsing.Labels.Statement.t = | Empty| OperatorAssignment of Verilog_parsing.Labels.AssignmentOperator.t| Labeled of Verilog_parsing.Common.identifier| BlockingAssignment| NonBlockingAssignment| Assign| Deassign| Force| Release| Case| Casex| Casez| Conditional| IncOrDec| SubroutineCall| SubroutineCallVoid| Disable| DisableFork| EventTrigger| EventTriggerNonBlocking| Forever| Repeat| While| For| Do| Foreach| Return| Break| Continue| ParBlock of Verilog_parsing.Common.identifier * Verilog_parsing.Labels.JoinSpec.t| ProceduralTimingControl| SeqBlock of Verilog_parsing.Common.identifier| Wait| WaitFork| WaitOrder| ProceduralAssertion| ClockingDrive| Randsequence of Verilog_parsing.Common.identifier| Randcase| ExpectProperty| Expr of Verilog_parsing.Labels.Expression.t| PExpr of Verilog_parsing.Labels.PropertyExpression.t
sectionYPositions = computeSectionYPositions($el), 10)"
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