package diffast-langs-verilog

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Module V_label.PropertyExpressionSource

include module type of struct include Ls.PropertyExpression end
Sourcetype t = Verilog_parsing.Labels.PropertyExpression.t =
  1. | Not
  2. | Strong
  3. | Weak
  4. | ImplicationOverlapped
  5. | ImplicationNonOverlapped
  6. | SharpMinusSharp
  7. | SharpEqSharp
  8. | Nexttime
  9. | S_nexttime
  10. | Always
  11. | S_always
  12. | Eventually
  13. | S_eventually
  14. | Until
  15. | S_until
  16. | Until_with
  17. | S_until_with
  18. | Implies
  19. | Iff
  20. | Accept_on
  21. | Sync_accept_on
  22. | Reject_on
  23. | Sync_reject_on
  24. | If
  25. | Case
  26. | Spec
Sourceval to_string : t -> string
Sourceval to_simple_string : t -> string
Sourceval to_tag : t -> string * 'a list
Sourceval get_identifier : 'a -> 'b
Sourceval to_short_string : t -> string