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A BIL model of CPU
In general this is a model of a processor architecture, involving ALU, processing unit, registers and memory.
The definitions in this module are so generic, that they present on all processors.
val gpr : Var.Set.t
A set of general purpose registers
val mem : var
Memory
val sp : var
Stack pointer
val zf : var
zero flag
val cf : var
carry flag
val vf : var
overflow flag
val nf : var
negative flag
val is_reg : var -> bool
is_reg var
true if var
is a processor register
val is_flag : var -> bool
is_flag reg
is true if reg
is a flag register
val is_sp : var -> bool
is_sp x = Var.same x sp
val is_bp : var -> bool
is_bp x
is true if x
can be possibly used as a base pointer register.
val is_zf : var -> bool
is_zf x = Var.same x zf
val is_cf : var -> bool
is_cf x = Var.same x cf
val is_vf : var -> bool
is_vf x = Var.same x vf
val is_nf : var -> bool
is_nf x = Var.same x nf
val is_mem : var -> bool
is_mem x = Var.same x mem