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package hardcaml
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type signal_op =
  1. | Signal_add
  2. | Signal_sub
  3. | Signal_mulu
  4. | Signal_muls
  5. | Signal_and
  6. | Signal_or
  7. | Signal_xor
  8. | Signal_eq
  9. | Signal_not
  10. | Signal_lt
  11. | Signal_cat
  12. | Signal_mux
type uid = int64
module UidMap : sig ... end
module UidSet : sig ... end
type signal_id = {
  1. s_id : uid;
  2. mutable s_names : string list;
  3. s_width : int;
  4. mutable s_deps : signal list;
}
and signal =
  1. | Signal_empty
  2. | Signal_const of signal_id * string
  3. | Signal_op of signal_id * signal_op
  4. | Signal_wire of signal_id * signal ref
  5. | Signal_select of signal_id * int * int
  6. | Signal_reg of signal_id * register
  7. | Signal_mem of signal_id * uid * register * memory
  8. | Signal_inst of signal_id * uid * instantiation
and register = {
  1. reg_clock : signal;
  2. reg_clock_level : signal;
  3. reg_reset : signal;
  4. reg_reset_level : signal;
  5. reg_reset_value : signal;
  6. reg_clear : signal;
  7. reg_clear_level : signal;
  8. reg_clear_value : signal;
  9. reg_enable : signal;
}
and memory = {
  1. mem_size : int;
  2. mem_read_address : signal;
  3. mem_write_address : signal;
}
and instantiation = {
  1. inst_name : string;
  2. inst_generics : (string * parameter) list;
  3. inst_inputs : (string * signal) list;
  4. inst_outputs : (string * (int * int)) list;
  5. inst_lib : string;
  6. inst_arch : string;
}
and parameter =
  1. | ParamString of string
  2. | ParamInt of int
  3. | ParamFloat of float
  4. | ParamBool of bool
val uid : signal -> uid
val depo : signal -> < data : signal list ; op1 : signal ; op2 : signal * signal ; sel : signal >
val deps : signal -> signal list
val names : signal -> string list
val width : signal -> int
val is_reg : signal -> bool
val is_mem : signal -> bool
val is_inst : signal -> bool
val is_const : signal -> bool
val is_select : signal -> bool
val is_wire : signal -> bool
val is_op : signal_op -> signal -> bool
val const_value : signal -> string
val new_id : unit -> uid
val reset_id : unit -> unit
val make_id : int -> signal list -> signal_id
val string_of_op : signal_op -> string
val to_string : signal -> string
val structural_compare : ?check_names:bool -> ?check_deps:bool -> signal -> signal -> bool