package hardcaml_xilinx_reports

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package hardcaml_xilinx_reports
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Module Hardcaml_xilinx_reportsSource

Run Vivado and create a synthesis timing and utilization report for a design.

Sourcemodule Clock : sig ... end

Define properties of clocks on the top level module. The most important properties are the clock net name and it's period.

Sourcemodule Command : sig ... end

Generate a generic command line for performing synthesis runs over a given design.

Sourcemodule Primitive_group : sig ... end

Primitive group definitions for Xilinx Vivado Ultrascale designs. See ug974.

Sourcemodule Project : sig ... end

Vivado synthesis project generation.

Sourcemodule Report : sig ... end

Reading of report files generated by the synthesis project.

Sourcemodule Wrap_with_registers : sig ... end