package hardcaml_xilinx_reports

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package hardcaml_xilinx_reports
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Module Hardcaml_xilinx_reports.Wrap_with_registersSource

Instantiate one more more circuits, wrapping the input and output ports with registers.

This can then be used to generate a synthesis report with accurate timing numbers (including input and output delays) using the blackbox=none and hier=true synthesis flow.

Sourcemodule type Sequential_interface = sig ... end