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package hardcaml_xilinx_reports
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Module Io.VariantsSource

Sourceval input_buffer : t Variantslib.Variant.t
Sourceval bidir_buffer : t Variantslib.Variant.t
Sourceval weak_driver : t Variantslib.Variant.t
Sourceval output_buffer : t Variantslib.Variant.t
Sourceval metastability : t Variantslib.Variant.t
Sourceval fold : init:'acc__0 -> bitslice:('acc__0 -> t Variantslib.Variant.t -> 'acc__1) -> dci_reset:('acc__1 -> t Variantslib.Variant.t -> 'acc__2) -> input_buffer:('acc__2 -> t Variantslib.Variant.t -> 'acc__3) -> delay:('acc__3 -> t Variantslib.Variant.t -> 'acc__4) -> bidir_buffer:('acc__4 -> t Variantslib.Variant.t -> 'acc__5) -> serdes:('acc__5 -> t Variantslib.Variant.t -> 'acc__6) -> weak_driver:('acc__6 -> t Variantslib.Variant.t -> 'acc__7) -> output_buffer:('acc__7 -> t Variantslib.Variant.t -> 'acc__8) -> sdr:('acc__8 -> t Variantslib.Variant.t -> 'acc__9) -> metastability:('acc__9 -> t Variantslib.Variant.t -> 'acc__10) -> ddr:('acc__10 -> t Variantslib.Variant.t -> 'acc__11) -> latch:('acc__11 -> t Variantslib.Variant.t -> 'acc__12) -> 'acc__12
Sourceval map : t -> bitslice:(t Variantslib.Variant.t -> 'result__) -> dci_reset:(t Variantslib.Variant.t -> 'result__) -> input_buffer:(t Variantslib.Variant.t -> 'result__) -> delay:(t Variantslib.Variant.t -> 'result__) -> bidir_buffer:(t Variantslib.Variant.t -> 'result__) -> serdes:(t Variantslib.Variant.t -> 'result__) -> weak_driver:(t Variantslib.Variant.t -> 'result__) -> output_buffer:(t Variantslib.Variant.t -> 'result__) -> sdr:(t Variantslib.Variant.t -> 'result__) -> metastability:(t Variantslib.Variant.t -> 'result__) -> ddr:(t Variantslib.Variant.t -> 'result__) -> latch:(t Variantslib.Variant.t -> 'result__) -> 'result__
Sourceval make_matcher : bitslice: (t Variantslib.Variant.t -> 'acc__0 -> (Base.Unit.t -> 'result__) * 'acc__1) -> dci_reset: (t Variantslib.Variant.t -> 'acc__1 -> (Base.Unit.t -> 'result__) * 'acc__2) -> input_buffer: (t Variantslib.Variant.t -> 'acc__2 -> (Base.Unit.t -> 'result__) * 'acc__3) -> delay: (t Variantslib.Variant.t -> 'acc__3 -> (Base.Unit.t -> 'result__) * 'acc__4) -> bidir_buffer: (t Variantslib.Variant.t -> 'acc__4 -> (Base.Unit.t -> 'result__) * 'acc__5) -> serdes: (t Variantslib.Variant.t -> 'acc__5 -> (Base.Unit.t -> 'result__) * 'acc__6) -> weak_driver: (t Variantslib.Variant.t -> 'acc__6 -> (Base.Unit.t -> 'result__) * 'acc__7) -> output_buffer: (t Variantslib.Variant.t -> 'acc__7 -> (Base.Unit.t -> 'result__) * 'acc__8) -> sdr: (t Variantslib.Variant.t -> 'acc__8 -> (Base.Unit.t -> 'result__) * 'acc__9) -> metastability: (t Variantslib.Variant.t -> 'acc__9 -> (Base.Unit.t -> 'result__) * 'acc__10) -> ddr: (t Variantslib.Variant.t -> 'acc__10 -> (Base.Unit.t -> 'result__) * 'acc__11) -> latch: (t Variantslib.Variant.t -> 'acc__11 -> (Base.Unit.t -> 'result__) * 'acc__12) -> 'acc__0 -> (t -> 'result__) * 'acc__12
Sourceval to_rank : t -> Base.Int.t
Sourceval to_name : t -> Base.String.t